The AVR series consists of a fairly broad range of hybrid-bit-width microcontrollers (nominally 16-bit code word, 8-bit data bus and ALU) sharing a common instruction set and differing primarily in the on-chip peripherals and package options. These devices don’t show a clear genealogical relationship to any other microcontroller core I’m aware of, but some variants do show superficial signs of having been designed for people migrating away from the 8051 (the 40-pin AVRs are in a very similar pinout to a standard 40-pin 8051, for instance). AVR is a Harvard- architecture RISC core with 32 8-bit general-purpose registers, named R0—R31.
These registers are mapped into the core’s data address space at address $00-$1F. Registers R26—R31 have a secondary function for indirect addressing modes; they are divided into pairs named X (R26—R27), Y (R28—R29) and Z (R30—R31). Any of these three paired registers can be used as a 16-bit pointer into data RAM (the first register named is, in each case, the less significant byte of the address word). Most instructions can operate on any register; a few instructions (such as word-add, wordsubtract, and load immediate) can operate only on a subset of the registers, R16—R31. The AVR core also has a separate 64-byte I/O address space to interface with the on-chip peripherals. All of these peripheral control registers are conveniently mirrored in the general data address space at locations $20-$5F, so that you can access them with different addressing modes if you wish. The ATtiny26L also has 128 bytes of SRAM from $60-$DF, and the remainder of the data address space is unimplemented.
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